1. Field of the Invention
The present invention relates to a type of semiconductor memory called an EEPROM (electrically erasable programmable read-only memory) device that allows rewriting of data to be performed individually in each memory cell.
2. Description of the Prior Art
An EEPROM device includes a number of memory cells each composed of, as shown in FIG. 7, a MOS-type FET (hereafter referred to as the "memory transistor") MT having a floating gate (a gate that is insulated from the surroundings) between a control gate CG and a conducting channel formed between a drain D.sub.M and a source S.sub.M within a silicon substrate, and a MOS-type FET (hereafter referred to as the "selection transistor") ST. To achieve storage of data, an EEPROM device exploits the fact that the threshold voltage of the memory transistor MT with respect to the control gate CG varies with the amount of electric charge accumulated in the floating gate FG. Note that part of the insulator (oxide film) between the floating gate FG and the drain D.sub.M is made thinner than its remaining part so that, by way of this thin part, electrons are injected into and expelled out of the floating gate FG by the tunnel effect.
The amount of electric charge accumulated in the floating gate FG of the memory transistor MT is usually so controlled that, as shown in FIG. 8, the threshold voltage of the memory transistor MT falls within one of two ranges that correspond to values "0" and "1" respectively. In this way, one bit of data is stored in each memory cell.
Note that, to read data from a memory cell of a one-bit-per-cell type as described above, it is necessary to prepare, as a voltage to be applied to the control gate CG of the memory transistor MT, a reference voltage E (see FIG. 8) that is approximately intermediate between the above-mentioned two ranges of the threshold voltage.
In recent years, to cope with demand for larger storage capacity, much research has been done in the field of so-called multivalued storage that aims to store two or more bits of data in one memory cell. For example, by controlling the amount of electric charge accumulated in the floating gate FG of the memory transistor MT in such a way that, as shown in FIG. 9, the threshold voltage of the memory transistor MT falls within one of four ranges that correspond to values "00", "01", "10", and "11" respectively, it is possible to store two bits of data in one memory cell.
Note that, to read data from a memory cell of a two-bits-per-cell type as described above, it is necessary to prepare, as voltages to be applied to the control gate CG of the memory transistor MT, a first reference voltage E1, a second reference voltage E2, and a third reference voltage E3 (see FIG. 9) that are approximately intermediate between the above-mentioned four ranges of the threshold voltage.
In an EEPROM device, writing of data to a memory cell is performed in the following manner. First, a high-level voltage (for example, 15 V) is applied to the gate G and the drain D.sub.S of the selection transistor ST, with the control gate CG of the memory transistor MT grounded and with the source S.sub.M of the memory transistor MT kept open (i.e. non-connected). This causes electrons to be expelled out of the floating gate FG of the memory transistor MT.
To control the amount of electric charge accumulated in the floating gate FG in accordance with the data to be written in, whereas the high-level voltage applied to the gate G and the drain D.sub.S of the selection transistor ST is kept constant regardless of the data to be written in, the duration of data writing is varied in accordance with the data to be written in.
Specifically, the longer the data writing duration, the greater the number of electrons expelled out of the floating gate FG and therefore the more the threshold voltage of the memory transistor MT drops. In contrast, the shorter the data writing duration, the smaller the number of electrons expelled out of the floating gate FG and therefore the less the threshold voltage drops.
Note that, before writing of data, erasing is performed. This causes a predetermined amount of electric charge to be accumulated in the floating gate FG and thereby makes rewriting of data possible.
As described above, in a conventional EEPROM device, the duration of data writing is controlled in accordance with the data to be written in. However, a process that depends on control of duration tends to cause unduly large variations in the distribution of the threshold voltage of the memory transistor MT, leading in some cases to garbled data. Moreover, controlling the duration of data writing naturally results in longer writing times with particular types of data than with other types of data, and thus, on the whole, requires longer writing times.
These inconveniences of a conventional EEPROM device are becoming increasingly intolerable as multivalued storage technology advances, that is, as more and more bits of data are stored in one memory cell.